Increasing Instruction Fetch Energy-eeciency of a Vlsi Microprocessor

VLSI devices with high power demands have several important drawbacks; power to run the chip must be supplied externally, and power is dissipated as heat, which must be removed from the circuit. Processor architects tend to view these issues as circuit technology or packaging problems. However, these solutions are limited, and do not necessarily provide insight into more direct approaches to energy-eecient architecture. In this paper, we present a model for estimating dynamic instruction fetch energy dissipation for CMOS microprocessors as a function of architectural parameters, cache events, and instruction traac. Starting with a parameterized baseline design for a simple pipelined RISC, we use the model and software simulation to explore the energy-budget implications of architectural and cache design decisions. We evaluate two instruction set encodings that yield signiicantly diierent density and traac, and show how increased code density, a cache block buuering scheme, and sub-blocking each can be used to reduce the instruction fetch energy budget.